Transistor protective circuit

ABSTRACT

A protective circuit for a transistor which limits the maximum allowable collector power loss so as to prevent the transistor from being destroyed is disclosed. A second transistor is connected in circuit with the main transistor to control the power loss in the main transistor. In one embodiment the protective transistor has a linear response and in another embodiment the protective circuit has a different slope in different operating ranges.

United States Patent Suzuki [451 July 18, 1972 l TRANSISTOR PROTECTIVE CIRCUIT 3,564,338 2/1971 Teshirosi et al ..3|1/31 [72] Inventor: T l sum, ToYko'JaPan 3,262,016 7/1966 Martin ..317/33 [73] Assignee: Sony Corporation, Toyko, Japan Primary Examiner-Nathan Kaufman Filed: D AXIOM-Hill, Sherman, Meroni, GPOQ & Simpson [21] Appl. No.: 96,287 [57] ABSTRACT Related US. Application Data A protective circuit for a transistor which limits the maximum [63] Cuminuation of Sci, No 775 386 Nov 1 3 1968 allowable collector power loss so as to prevent the transistor abandone from being destroyed is disclosed. A second transistor is connected in circuit with the main transistor to control the power 52 us. or. .330/207 P, 330/24, 330/26 in the main transismf- Pmmctive 51 Int. Cl. 1103127100, H03t 1/38 transistor has a linear response and in Math" embodiment 58 Field oiSearch .307 202; 330 207 P the protective circuit has a different slope in different p ing ranges. [56] Reierenoes Cited 4 Claims, 13 Drawing Figures UNITED STATES PATENTS 3,5002 I 8 3/1970 Burwen ..330/207 P PAIENIEIJwusmz 3,573,40

SHEET 2 [IF 2 LYVEQNTOR 0 sbzum TRANSISTOR PROTECTIVE CIRCUIT This application is a continuation of Ser. No. 775,386 filed Nov. 13, 1968 and now abandoned.

BACKGROUND OF THE INVENTION This invention relates in general to circuits for protecting transistors and in particular to a transistor protective circuit utilizing a current limiter.

DESCRIPTION OF THE PRIOR ART In transistors the power loss at the collector heats the junctions of the transistors and can destroy the transistors when the temperature exceeds a predetermined value.

The maximum allowable power loss at the collector is substantially constant and when the collector voltage rises in an emitter-grounded transistor, for example, the collector power loss is likely to exceed the maximum pemu'ssive value and damage the transistor unless the collector current is decreased. For example, in a transistorized single ended pushpull circuit, commonly referred to as a SEPP circuit, that has its load short-circuited will have only an output coupled capacitor as the load. Such a load will have an impedance close to zero and will be reactive and will shift the phase relationship between the collector voltage and the collector current such that when the collector voltage is at a maximum with respect to a low input, the maximum collector current will flow and will cause the collector power loss to exceed its safe range.

It has been proposed in the prior art to utilize a current limiter for holding the collector current within its desired range even under such conditions. A current limiter serves to hold the collector current below a certain maximum value independent of the collector voltage and under certain conditions holds the collector power loss within a safe range. when an inductive load such as a speaker coil, for example, of about 4 ohms is connected in series to the output coupling capacitor in a SEPP circuit, there is no possibility ofintroducing a phase shift between the collector voltage and the collector current to insure that the transistor operates even if the collector current exceeds the operating current value of the current limiter. Also, the use of a current limiter limits the maximum output attainable at the load. Also, even if the collector current is lower than the value set by the current limiter, if the collector voltage goes up the collector power loss may exceed its maximum value and result in destruction of the transistor because the current limiter does not prevent such breakage.

SUMMARY OF THE INVENTION Ideal protection of a transistor is obtained by the use of a current limiter which has a characteristic so that its current limiting value increases when the collector voltage is low and decreases when the collector voltage is high. This means that the operating point of the current limiter must vary with the collector voltage.

It is an object of the present invention to provide a transistor protective circuit which employs a current limiter that varies the limiting level as a function of the voltage applied to the main transistor to be protected. In one embodiment a transistor amplifier is connected with a limiting transistor such that the limiting transistor adjusts the limiting current of the transistor amplifier to prevent injury to the transistor.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a graph illustrating voltage-current characteristic curves for this invention;

FIG. 2 is a schematic view of the invention;

FIG. 3 is a schematic ofa modification of the invention;

FIG. 4 is a schematic ofa further modification of the invention;

FIG. 5 is a schematic view of a modification of the inven tion;

FIG. 6 is a schematic view of a modification of the invention;

FIG. 7 is a schematic view of a modification of the invention;

FIG. 8 is a schematic view of a modification of the invention;

FIG. 9 is a schematic view of a modification of the invention;

FIG. 10 is a schematic view of a modification of the invention;

FIG. 11 is a schematic view of a modification of the invention;

FIG. I2 is a schematic view of a modification of the invention; and

FIG. 13 is a schematic view of a modification of the invention illustrating a single-ended push-pull amplifier.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Various circuits have been proposed for protecting transistors from overload such as the so-called SEPP circuit which employs a current limiting circuit. For example, in FIG. 1 numeral 1 represents a load line, dotted curve 2 represents the maximum permissible collector power loss (Pc curve). Curve 3 represents a current limiting level. Prior art current limiting circuits are incorporated in SEPP circuits so as to prevent the current from going above the level defined by curve 3 which holds the maximum power loss at P, where curve 3 crosses curve 2. The voltage V, represents the power source voltage at point P, and the voltage at the connection point of the transistors for deriving a load voltage is V A current limiting circuit holds the output of the SEPP circuit less than a value defined by point P where load curve I Crosses current limiting level 3. When the collector power loss enters into a range higher than the point P,, defined by the curves 2 and 3, it is possible that the current limiting circuit will not prevent damage to the transistors.

The present invention prevents damage to a transistor. For example, FIG. 2 illustrates a main transistor T, which is to be protected and which is shown as NPN-ty e transistor, for example. The transistor T, has its base connected to an input terminal t and has its collector connected to an output terminal t and to a power source terminal I, through a load resistor R, A control transistor T has its collector connected to the base of transistor T, and its base is connected to a junction point between resistors R, and R, that are connected between the collector and emitter of the transistor T,. The emitter of transistor T is connected to a terminal r which is connected through the resistor R to the emitter of the transistor T,. The base of the control transistor T is supplied through resistor R, a voltage related to the collector current of the main transistor T,.

During normal operation, the control transistor T is in the off state and does not conduct. However, when the collector power loss of the main transistor T, exceeds its given limit range, the control transistor T becomes conductive to control the base current flowing to the transistor T, to decrease its collector current, thus protecting the transistor T, from damage. If the collector current and voltage between the collector and emitter of the main transistor T, are designated as l, and V respectively and the voltage between the base and emitter of the control transistor T is designated as V, it follows that:

Thus, when the voltage V equals zero, a current of V /R flows, and the value of the current being controlled decreases as the collector voltage increases with a Slope of R,,jR (R, R This is indicated by the straight line 7 of FIG. I.

Thus, an approximation of the straight line 7 to the curve 2 will increase the working range of the main transistor T,. For example, in the case of an SEPP circuit, the main transistor can be driven up to point P, where the load curve I crosses the straight line so that its output will be increased correspondingly.

If the terminal I, is connected to the connection point between the base of the main transistor T, and the collector of the transistor T,, and the terminal I is connected to the collector of the transistor T, and the terminal i is connected to the connection point between the emitter of the transistor T, and the resistor R and if the terminals I and i are considered as analogous to the base, collector and emitter electrodes of a transistor, the protective circuit may be applied to other transistor circuits.

Although the current limiting efiect is produced by the straight line 7 which approximates the permissible collector power los curve 2 by the circuitry of FIG. 2, a more accurate approximation may be made by a line having two parts with different slopes. Such a characteristic is obtained with the circuit of FIG. 3. In FIG. 3, elements similar to those in FIG. 2 are identified by the same reference numerals and characters. A resistor R, is connected between terminal i and the resistor R, and the resistor R and the diode 10, such as a Zener diode, is connected between the emitter of transistor T, and the junction point between resistors R, and R,,.

In the circuit of FIG. 3, when the voltage between the collector and emitter of the main transistor T, is low, the Zener diode will stay in the off state and the circuit will operate similar to the circuit of FIG. 2. In other words, the collector current I decreases relatively abruptly with an increase in the collector-emitter voltage V When the collector voltage V, exceeds a certain value, the Zener diode 10 will become conductive due to the Zener effect and a constant voltage will be applied to the base of the control transistor T and at the same time a voltage related to the collector current I will be fed to the base of the transistor T,. In this range the collector voltage-current characteristics of the main transistor T will have a relatively general slope. If the voltage across the Zener diode I0 is designated as V,. when:

This is illustrated as curve II in FIG. I which has two parts. Thus, when the collector voltage V is low, the curve I I has a relatively steep slope but when the collector voltage V is above a value of the curve takes on a gentler slope close to curve 2.

FIG. 4 illustrates a modification of the circuit of FIG. 2 in which a diode 12 is connected between the base of the transistor T, and the collector of the transistor T The diode I2 will prevent current from flowing from the base of the transistor T, to the collector when the main transistor T, is non-conductive.

The diode I2 may be replaced with a third transistor T, as shown in FIG. 5 to prevent the unwanted conduction of the transistor T, and the composite h of the transistors T, and T, rises to provide for improved control efficiency.

FIG. 6 illustrates a further modification wherein a fourth transistor T, is connected in circuit with the transistor T to provide a Darlington connection. FIG. 7 illustrates transistors T, and T, which are of different conductivity types connected in a Darlington circuit.

FIGS. 8 through I2 are the equivalent circuits PNP-type transistors instead of the NPN-types illustrated in FIGS. 2 and 4-7. For example, the circuit in FIG. 8 has transistors T, and T, which are PNP-types and the circuit operates as the circuit of FIG. 2. The circuit of FIG. 9 corresponds to the circuit of FIG. 4 except the transistors T, and T, are PNP-types. The circuit of FIG. 10 corresponds to the circuit of FIG. 5 except the transistors T,', T, and T, are PNP-types instead of NPNs.

The circuit of FIG. 12 corresponds to the circuit of FIG. 7 except the types of the transistors T, through T, are different types than in FIG. 7.

FIG. 13 illustrates a semi-complementary SEPP circuit which has transistors T,,, T,, T, and T, where the NPN-type transistor T, and the PNP-type transistor T and respectively, connected to the NPN-type transistors T and T The transistors T, and T, are driven by a common driving transistor T,. The driving transistor T, is connected to a power supply terminal I5 through a bias supply comprising the diodes I3 and a resistor R.,. An input terminal I61 is connected to the base of transistor T, and an output terminal I is coupled through a capacitor 17 to the collector of the transistor T,,. The transistor T,,, is connected as a control transistor for the transistor T,. A resistor R,, is connected to the connection point between the transistors T, and T, and the capacitor I7v A pair of voltage dividing resistors R, and R, are connected across the resistor R,,. The emitter of transistor T,, is connected to the connection point between resistors R, and R,,. The collector of the transistor T is connected to the base of transistor T, through a diode 20 connected in a forward direction relative to the transistor T,,,.

A pair of resistors R, and R, are connected between the connection point between transistors T, and T, and the power supply terminal IS. The junction point between resistors R, and R, is connected to the base of the transistor T,,,. A transistor T,, is connected to protect the transistor T, and the emitter of the transistor T,, is connected to the base of the transistor T, and its collector is connected to the connection point between the capacitor I7 and the resistor R,,.

The base of the transistor T,, is connected to the collector of a transistor T,, which has its emitter connected to the connection point between resistors R and R,,. The base of transistor T, is connected to the connection point of resistors R and R which are connected from the connection point of the transistors T, and T and ground. In the circuit of FIG. B when either of the transistors T, and T is conductive the other is non-conductive and a reverse voltage is applied between the base and emitter of the non-conductive transistor. The diode 20 is connected in series with the protective control transistor T or the transistor T 1 of opposite polarity to transistor T,, is connected to the transistor T,, to prevent lowering of the input impedance. The voltage dividing resistors R and R,

which are connected in parallel with resistor R correspond to resistor R in FIG. 2 and a voltage is produced across the resistor R which is fed to the transistors T and T The protective circuit of this invention allovis the efficient use of transistors and eliminates the destruction of transistors due to overload. Apparatus according to this invention has been constructed and tested and the output of an amplifier which previously produced 50W was safely raised to a level of 100W by the use of the invention described herein.

It will be apparent that many modifications and variations may be effected without departing from the scope of the novel concepts of this invention.

1 claim as my invention:

1. A protective circuit for protecting a main transistor which receives an input signal on its base from an input terminal comprising:

a unilateral current device;

a second transistor connected with its emitter and collector in series with the unilateral current device between the base of the main transistor and an output terminal;

three resistors connected in series between the collector and emitter of the main transistor and developing a voltage proportional to the voltage between the emitter and collector of the main transistor;

the base of the second transistor connected to the junction point between the one of said three resistors connected to the collector of said main transistor and the second of said three resistors to receive a signal indicative of the voltage between the emitter and collector of the main transistor;

a fourth resistor connected to the emitter of said second transistor and to the junction point between said second and third resistors so as to supply a voltage proportional to the collector current of the main transistor to the second transistor such that when the voltage between the collector and emitter of the main transistor is low the collector voltage versus current characteristic of the main transistor will have a relatively steep slope and when the collector voltage exceeds a predetermined value the collector voltage versus current characteristic of the main transistor will have a relatively gentle slope.

2. A protective circuit according to claim 1 comprising a fifth resistor connected between the emitter of said second transistor and said output terminal.

3. A protective circuit according to claim 2 including a third transistor with its base connected to the emitter of said main transistor and its collector connected to the collector of said main transistor and a sixth resistor connected between the emitter of said third transistor and the junction point between said second and third resistors.

4 A protective circuit according to claim 3 including a fourth transistor of opposite type to said main transistor receiving said input signal on its base from said input terminal, seventh and eighth resistors connected in series between the emitter of said fourth transistor and said output temiinal, a fifth transistor with its collector connected to said output terminal and its emitter connected to the base of said fourth transistor, and the base of said fifth transistor connected to the junction point between said seventh and eighth resistors. 

1. A protective circuit for protecting a main transistor which receives an input signal on its base from an input terminal comprising: a unilateral current device; a second transistor connected with its emitter and collector in series with the unilateral current device between the base of the main transistor and an output terminal; three resistors connected in series between the collector and emitter of the main transistor and developing a voltage proportional to the voltage between the emitter and collector of the main transistor; the base of the second transistor connected to the junction point between the one of said three resistors connected to the collector of said main transistor and the second of said three resistors to receive a signal indicative of the voltage between the emitter and collector of the main transistor; a fourth resistor connected to the emitter of said second transistor and to the junction point between said second and third resistors so as to supply a voltage proportional to the collector current of the main transistor to the second transistor such that when the voltage between the collector and emitter of the main transistor is low the collector voltage versus current characteristic of the main transistor will have a relatively steep slope and when the collector voltage exceeds a predetermined value the collector voltage versus current characteristic of the main transistor will have a relatively gentle slope.
 2. A protective circuit according to claim 1 comprising a fifth resistor connected between the emitter of said second transistor and said output terminal.
 3. A protective circuit according to claim 2 including a third transistor with its base connected to the emitter of said main transistor and its collector connected to the collector of said main transistor and a sixth resistor connected between the emitter of said third transistor and the junction point between said second and third resistors. 4 A protective circuit according to claim 3 including a fourth transistor of opposite type to said main transistor receiving said input signal on its base from said input terminal, seventh and eighth resistors connected in series between the emitter of said fourth transistor and said output terminal, a fifth transistor with its collector connected to said output terminal and its emitter connected to the base of said fourth transistor, and the base of said fifth transistor connected to the junction point between said seventh and eighth resistors. 